1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device having, in a semiconductor chip thereof, a voltage generating circuit for generating operation voltage required for an integrated circuit thereof, a method of investigating a cause of a failure if the failure takes place in the semiconductor integrated circuit device, and a method of verifying the operation of the semiconductor integrated circuit device.
2. Description of the Related Art
An EEPROM, which is one of non-volatile memories, permits data to be electrically written thereto and data to be electrically erased therefrom. A portion of EEPROM, for example, an EEPROM called NAND EEPROM, uses a tunnel current when data is electrically written or erased. The NAND EEPROM has a plurality of memory cells (hereinafter called xe2x80x9ccellsxe2x80x9d) serially connected between bit lines and the ground lines. A portion of the NAND EEPROM comprises, in the chip thereof, a voltage generating circuit for generating writing/erasing voltage, the level of which is higher than the power supply voltage. The NAND EEPROM can be operated by only supplying one type of power supply voltage.
FIGS. 28A to 28C show a cell of the NAND EEPROM. FIG. 28A is a plane view, FIG. 28B is a cross-sectional view taken along line Bxe2x80x94B shown in FIG. 28A, and FIG. 28C is a cross-sectional view taken along line Cxe2x80x94C shown in FIG. 28A.
FIG. 28A shows two cells, in series, connected to each other. Then, the structure of the cell will now be described while paying attention to one of the two cells.
As shown in FIGS. 28A to 28C, an N-type silicon substrate 1 includes a Pxe2x88x92type well 2 formed therein. The well 2 includes a plurality of N+type diffusion layers 3 formed therein. The N+type diffusion layers 3 serve as sources and drains of the cell. A portion of the substrate 1 between the N+type diffusion layers 3 is used as a channel region 4. On the channel region 4, there is formed a gate oxide film (SiO2) 5. Note that a thick silicon dioxide film (SiO2) 6 formed on the well 2 is a field insulating film for separating the cells from one another. The field insulating film 6 is formed by LOCOS (Localized Oxidation of Silicon) A floating gate 7 is formed on the top surface of the gate oxide film 5 to the field insulating film 6. The floating gate 7 is made of electrically conductive polysilicon. The floating gate 7 is a charge storage layer for enabling the threshold of the cell to be variable. Therefore, the floating gate 7 is formed for each cell. On the floating gate 7, there is formed a control gate 9 through an interlayer insulating film (SiO2). The control gate 9 is made of electrically conductive polysilicon. The control gate 9 serves as a word line.
The method for writing data xe2x80x9c0xe2x80x9d in the cell will now be described.
The well 2 and the N+type diffusion layers 3 respectively are grounded, and then program potential VPP (about 20V) is applied to the control gate 9. As a result, the control gate 9 and the floating gate 7 are capacity-coupled to each other so that the potential of the floating gate 7 is raised. The conduction type of the channel region 4 is reversed from P type to N type. The N-type channel region 4 is connected to the N-type diffusion layer 3. The potential of the channel region 4 is made to be the ground potential. Thus, the potential difference takes place between the channel region 4, which has been made to be the ground potential, and the floating gate 7. Therefore, a tunnel current flows from the floating gate 7 to the channel region 4 (and the N+type diffusion layers 3). When the tunnel current has been allowed to flow, electrons are injected into the floating gate 7. The floating gate 7, into which electrons have been injected, is negatively charged. When the floating gate 7 has been negatively charged, the threshold of the cell is raised. When the threshold of the cell has been raised, the cell is turned off when data is read out. The foregoing state is a state in which data xe2x80x9c0xe2x80x9d has been written. When data is read out, the state in which the cell has been turned on, is a state in which data xe2x80x9c1xe2x80x9d has been written. In this specification, the method of writing data xe2x80x9c1xe2x80x9d is omitted from description.
The magnitude of the tunnel current depends upon the level of the potential between the floating gate 7 and the channel region 4. Since change in the magnitude of the tunnel current causes the amount of electrons to be injected into the floating gate 7 to be changed, the amount of charge of the floating gate 7 is changed. That is, even if the same program potential VPP is applied to the control gate 9, change in the intensity of the electric field E results in the threshold of the cell being changed.
The electric field E is represented by the following equation:
E={CCF/(CCF+CFS)}xc3x97(1/tGAOX)xc3x97Vxe2x80x83xe2x80x83(1)
wherein CCF is the capacity of a capacitor between the control gate 9 and the floating gate 7, CFS is the capacity of the capacitor between the control gate 9 and the channel region 4, tGAOX is the thickness of the gate oxide film 5 and V is the voltage to be applied to the control gate 9.
An assumption is performed that a capacitor having capacity CCF and a capacitor having capacity CFS are parallel-plate type capacitors respectively having areas SCF and SFS . Moreover, thickness of the interlayer insulating film 8 is assumed to be tINTER.
Assuming that the gate oxide film 5 and the interlayer insulating film 8 are made of the same material (SiO2) having the same dielectric constant, the foregoing Equation (1) can be converted into the following equation:
E=(V/tGAOX)xc3x97[1/{1+(SFS/SCF)xc3x97(tINTER/tGAOX)}]xe2x80x83xe2x80x83(2)
As can be understood from Equation (2), the electric field E is in inverse proportion to the thickness tGAOX and the area SFS. The area SFS is determined by gate width W shown in FIG. 28B and gate length L shown in FIG. 28C.
The thickness tGAOX of the gate oxide film 5 is determined in an oxidizing process for forming the gate oxide film 5. The gate length L is determined in a lithography process for patterning the control gate 9 and the floating gate 7. That is, each of the thickness tGAOX, the gate width W and the gate length L unintentionally contains dispersion (dispersion occurring during the manufacturing process) from a designed value. Since each of the thickness tGAOX, the gate width W and the gate length L contains dispersion from the designed value as described above, the electric field E cannot be constant for all chips.
However, since the voltage V is fixed for all chips, the quantity of electrons to be injected into the floating gate 7 is dispersed for each chip.
The dispersion becomes greatest for each manufacturing lot because the same manufacturing conditions cannot be allowed to reappear for all lots even if the manufacturing process is performed on the same manufacturing line.
To prevent dispersion in the quantity of electrons to be injected into the floating gate 7, it might be considered to feasible to employ a contrivance with which the voltage to be applied to the control gate 9 is made to be variable for each chip. The voltage to be applied to the control gate 9 is set by using a fuse. However, the method of setting the voltage by using the fuse cannot enable the set voltage level to easily be known after the semiconductor integrated circuit device has been packaged. To detect the set voltage level, the package is needed to be decomposed to take out the chip, followed by decomposing the chip to visually confirm whether the fuse has been disconnected.
If the integrated circuit device encounters a failure, investigation of the cause of the failure is a critical fact to significantly improve the reliability of the products and manufacturing yield of the same.
The causes of failures experienced with the integrated circuit device have not been limited to simple causes, such as short circuit and breakdown, as the structure of the integrated circuit device has been complicated. For example, the causes are exemplified by interference of circuits and a peculiar phenomenon occurring during the operation of the circuit, each of which cannot be expected at the time of designing the integrated circuit device.
Although the chip is, as a matter of course, decomposed to investigate the cause of the failure, the decomposition results in the device to be broken and, therefore, it cannot be operated anymore. Thus, interference of circuits and a peculiar phenomenon occurring during the operation of the circuit, each of which cannot be expected cannot be investigated.
In view of the foregoing, a first object of the present invention is to provide a semiconductor integrated circuit device capable of detecting a set internal voltage level without a necessity of decomposing the package and the chip even after the chip has been packaged and a method of investigating the cause of a failure in a semiconductor integrated circuit device using the foregoing semiconductor integrated circuit device.
A second object of the present invention is to provide a semiconductor integrated circuit device capable of previously verifying the operation of an integrated circuit at each set internal voltage level and a method of verifying the operation of a semiconductor integrated circuit device using the semiconductor integrated circuit device.
A third object of the present invention is to provide a semiconductor integrated circuit device having a circuit for setting the internal voltage level to be any one of variable levels, capable of minimizing the size of the circuit and thus having a small area.
To achieve the first object, a semiconductor integrated circuit device according to the present invention comprising: a semiconductor chip; an integrated circuit provided in the chip; an internal voltage generating circuit for generating an internal voltage used in the integrated circuit; an internal voltage setting circuit for setting a level of the internal voltage; and a level-setting information extracting circuit for extracting a level-setting information from the internal voltage setting circuit to the outside of the chip.
To achieve the second object, a semiconductor integrated circuit device according to the present invention comprising: a semiconductor chip; an integrated circuit provided in the chip; an internal voltage generating circuit for generating an internal voltage used in the integrated circuit; an internal voltage setting circuit for setting a level of the internal voltage; a determining circuit for determining the level of the internal voltage; and a changing circuit for changing the level of the internal voltage before the determining circuit determines the level of the internal voltage.
To achieve the third object, a semiconductor integrated circuit device according to the present invention comprising: a semiconductor chip; an integrated circuit provided in the chip; an internal voltage generating circuit for generating first and second internal voltages used in the integrated circuit; a first internal voltage setting circuit for setting a level of the first internal voltage; and a second internal voltage setting circuit for setting a level of the second internal voltage.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out in the appended claims.